In large electro-optical devices, a problem arises in respect of the power distribution to each of the pixels in the matrix. This power distribution is provided by power conducting planes which cover the surface of the pixel matrix and which are each connected to a power source at one or more electrical contact points distributed over the edges of the plane, generally via a flexible connector with low terminating impedance.
Since these conducting planes have to supply current to a large number of pixels simultaneously, their surface resistance leads in practice to voltage drops, which must be compensated for by applying a higher voltage than that which would normally suffice for driving an individual pixel.
The structure and the material or materials of the conducting planes are determined primarily by constraints which arise from the technology and topology of the device concerned, and which, notably, depend on whether or not the conducting plane is on a light transmission path, the location of the conducting plane in the stack of layers of the matrix, and particularly whether the conducting plane has to be formed on top of fragile layers, which rules out certain manufacturing processes such as high-temperature processes. All these constraints must be taken into account in the production of the conducting planes, while attempting to achieve the lowest possible resistance per unit of surface area. Other constraints may arise from the proposed applications: in lighting devices, the choice of conductive materials is constrained by the objective of very low cost, to the detriment of their conductivity.
A further constraint on large active matrices relates to the density of the address lines, which makes it impossible to provide points of connection to the power source along the whole periphery of the power conducting plane.
To aid the understanding of the last-mentioned problem, FIG. 1 shows a schematic illustration of an active pixel matrix pi,j. Each pixel pi,j comprises a pixel element and an associated elementary control circuit. Each pixel pi,j is conventionally positioned at the intersection of a row li and a column colj of the matrix (i is an integer varying from 1 to n, and j is an integer varying from 1 to m). The matrix is inscribed within a rectangular region denoted ZA, generally called an active zone. The addressing circuits SELX and SELY of the rows and columns are arranged on the periphery of this active zone ZA, along two adjacent edges b1 and b2, corresponding to the top and left-hand edge of the active zone ZA in the figure.
These addressing circuits SELX and SELY are connected to pixel address lines: the addressing circuit SELX drives the selection lines seli, each of which enables a corresponding row li of pixels to be selected; the addressing circuit SELY drives the data lines datj, each of which enables a display data element to be transmitted to a corresponding column colj of pixels; this data element is transmitted to the pixel element of the pixel pi,j at the intersection of the row li and the column colj, via the elementary control circuit (active matrix) of the pixel.
In the case of a large matrix, the density of the address lines seli and datj driven by the circuits SELX and SELY and the constraints associated with the required electrical performance of these circuits are such that the power supplies cannot be connected to the conducting planes via the edges along which these circuits are placed. Thus a conducting plane can be connected to a power source only via the two adjacent edges b3 and b4 which are opposite the edges b1 and b2 along which the addressing circuits are positioned.
This is shown schematically in FIG. 2. A power conducting plane P1 of rectangular shape covers the surface of the active zone ZA. It is connected to a voltage source ALIM which supplies a voltage VDD to be applied to each of the pixels of the matrix. Another conducting plane, or earth plane, not shown in FIGS. 1 and 2, supplies a common earth potential VSS to the pixels. The connection to the power source can be provided by one or more electrical contact points, shown as points c1, c2, c3 and c4 in the example, positioned on the periphery of the conducting plane P1, but only along the edges b3 and b4. The distance between each pixel power source varies according to the position of the pixel in the matrix: the resulting voltage drop is much more marked in the pixels located in the upper left-hand part of the matrix, such as pixel p1,1, which are farther from the contact points than those such as pixel pn,m, located in the lower right-hand part in the proximity of these points.
To compensate for the voltage drop in the pixels most remote from the points of connection to the power source, the voltage VDD supplied by the power source is set at a higher level than would normally be required to control a single pixel, in order to ensure that even the most remote pixels can be controlled and the desired luminance can be obtained.
The problem of voltage drops due to the intrinsic resistivity of the conducting plane supplying the voltage VDD is present in the same way on the earth plane side, if a sufficiently conductive earth plane cannot be formed: the pixels located remotely from the contact points receive a voltage of less than VDD, while also receiving a voltage greater than VSS from the other side; there is a risk that the voltage across their terminals will be less than a threshold below which the pixels can no longer emit light, if the emitting element is an organic or inorganic light-emitting diode.
These problems of power distribution are, notably, one of the obstacles to the development of active matrix OLED devices for large sizes, although the invention is applicable to inorganic LED matrices.
FIG. 3 shows a conventional diagram of a pixel pi,j of an active matrix OLED. The pixel pi,j comprises an organic light-emitting diode D(OLED), comprising, in practice, one or more diodes in series, and formed by a stack of organic layer(s) and an elementary control circuit based on thin film transistors (TFT) (T1 and T2) formed under the organic stack (on a transparent substrate), this circuit being driven by the respective address lines seli and datj. The concept of an active matrix corresponds to the set of elementary control circuits integrated into the matrix, one in each pixel region, by means of which the pixels are driven.
The elementary control circuit comprises:
a selection transistor T1, whose gate g1 is connected to a row selection line seli, and a source/drain electrode connected to a data line datj (using the notation conventions of FIGS. 1 and 2); and
a current control transistor T2 whose gate g2 is connected to the other source/drain electrode of the selection transistor T1. This control transistor T2 is connected in series with the diode D(OLED), between a supply voltage source VDD which can supply the current required for light emission and a reference potential VSS, connected to an electrical earth plane GND. In the example, one source/drain electrode of the control transistor T2 is thus connected to an electrode (the anode) of the diode, and the other is connected to the supply voltage source VDD.
A storage capacitance Cs is also generally provided between the gate g2 of the control transistor and the source/drain electrode that is not connected to an electrode of the diode. This capacitance keeps the display control voltage applied to the gate of the transistor T2 over the whole image frame (the selection lines being selected one by one in sequence).
The diagram of FIG. 3 is provided by way of example. It could be more complex and could incorporate devices for correcting non-uniformity or compensating for performance drift, but a branch with the OLED and the control transistor in series is present in all cases.
The pixel display command is executed as follows: the pixel pi,j is selected for display by the application of a selection signal on the line seli; the transistor T1 becomes conducting and transmits to the gate g2 of the control transistor T2 an applied control voltage on the line datj, corresponding to a display data element received for this pixel by the circuit SELY. The transistor T2 biased in this way draws a current i that flows through the diode, which can then emit a corresponding amount of light. This current is supplied by the electrical power source VDD and flows through the earth plane GND.
The current is thus supplied to the pixels by the two conducting planes located on either side of the organic stack forming the OLED diode. The upper conducting plane is formed on top of the organic stack. The lower conducting plane is commonly integrated and/or produced together with the thin layers forming the active matrix and therefore the transistors, the selection lines li and the data lines datj driving the control circuits.
Regardless of the type of emission (from top or bottom), the lower conducting plane may be made in the form of a thick metal grid, with a mesh corresponding to the pitch of the pixels so as to correspond to the active matrix topology. It is made of gate metal or source/drain metal, and therefore has a low resistance (0.2 ohms per square). Owing to the structure of the grid, however, the resistance per unit of actual surface area of this conducting plane is higher, by about 1 ohm per square for a surface occupancy of 20%. In the case of emission from the bottom, a compromise must be sought between the pixel aperture rate which is preferably as high as possible and the voltage drop on the pixels which is preferably minimized (as the aperture rate increases, the current density decreases, thereby increasing the voltage drop in the pixel).
The upper conducting plane is formed on the organic stack. When the emission is downward, this conducting plane does not have to be transparent. It is then typically formed as a thick metal layer, typically made of aluminium with a very low surface resistance.
In the case of upward emission, however, this conducting plane must be at least partially transparent. Because of the fragility of the organic layers, it is formed by vacuum evaporation through a mask. This conducting plane cannot be made in the form of a thick metal grid if this method is used. Thus the upper conducting plane has to have a solid plate structure which is conductive and at least partially transparent. Even if a transparent conductive oxide such as indium tin oxide (ITO) can be deposited at low temperature while retaining this material's properties of high transparency, at about 90%, these conditions of use do not allow good properties of electrical conductivity to be obtained. In practice, the best possible result is a resistance per unit of surface area of about 20 ohms per square.
Thus it is preferable to make the conducting plane in the form of a thin layer of a metal which is a very good conductor, for example gold. In this way, a transparent conducting plane (with a transmission of more than 80%) can be obtained, with a surface resistance of about 4 ohms per square.
Because of these various constraints concerning the light transmission, the fragility of the organic layers and the active matrix topology in these OLED screens, it is impossible to make conducting planes with sufficiently low resistance according to the prior art, especially in the case of upward light emission. In the case of downward light emission, the conducting planes are less resistive and may be structured in the form of a grid by photolithography before the deposition of the fragile OLED layers, but because of the active matrix, on the one hand, and the fact that they have to allow light to pass through, on the other hand, the grid can only occupy a fraction of the surface. The resistivity of the conducting plane increases in a way that is inversely proportional to its surface occupancy. Furthermore, it is necessary to compensate for the loss of emission surface by an increase in the luminous intensity emitted by the OLED, to obtain good luminance properties, which may have an effect on the service life.
In both cases, in order to avoid a loss of display luminance, it therefore becomes necessary to overdesign the electrical power sources VDD or VSS, so that the potential difference applied between the two conducting planes allows the diode and the current control transistor of each pixel of the matrix to be biased, regardless of the position of this pixel (identified by a selection line and a corresponding data line) in this matrix.
If this is done, the power budget is degraded. Furthermore, it has no effect on the non-uniform distribution of the voltage applied to the terminals of the pixels, and therefore on the gradation of the resulting luminance.
For example, let us consider an upwardly emitting OLED screen in which the OLED diode is formed by a stack of two or three colour diodes, providing white light emission. The supply voltage VDD must be defined so as to allow the OLED diode and the current control transistor to be biased to the conducting state, regardless of the displayed image, and notably when the image to be displayed is entirely white, corresponding to maximum current consumption in the diodes: in these conditions, the voltage drop in the conducting plane is also highest.
Typically, in the case of an OLED diode formed by a stack of two or three colour diodes, for emission in white, the bias voltage of the pixels (the diode and the control transistor) must therefore be at least 7.5 volts. To allow for the variations in threshold voltage, notably, a higher voltage setting is used, for example 10 volts.
Let us assume that a totally white image is to be displayed with a target brightness of 600 candelas per square meter on a large screen measuring 15.4 inches.
With an OLED diode having an efficiency of 20 candelas per ampere and an upper conducting plane having a surface resistance of 4 ohms per square, supplied via two adjacent edges (b3 and b4 in FIG. 2), it is actually necessary to provide a higher supply voltage VDD of 16 volts in order to obtain 10 volts between the electrodes of the pixel p1,1 located in the upper left-hand corner, opposite the two edges b3, b4. The power consumption is about 243 watts, which can be divided into 33 watts for the upper conducting plane supplying the voltage VDD (disregarding the voltage in the plane connected to earth) and 210 watts in the diodes. Assuming that it is possible to supply all the pixels uniformly, at the minimum voltage of 10 volts, the power consumption will be about 158 watts.
FIG. 4 shows the distribution of the supply voltage (VDD-VSS) at the terminals of the pixels as a function of their position in a matrix, and thus as a function of their distance from the points of connection of the conducting plane to the power source VDD (16 volts), and of their distance from the points of connection to the earth plane GND if the earth plane is equally resistive. This distribution, estimated on the basis of the modelling of the current consumption in each pixel, demonstrates the gradual loss over the pixels, as a function of the distance from the connection point to the voltage source, which is also manifested as a gradual loss of luminance.
In order to overcome this problem of the voltage drop in the conducting planes, some researchers are working on different pixel control systems, while others are seeking structures and materials for conducting planes that will enable their surface resistance to be reduced.